Processor Fundamentals
Inside the CPU: registers, buses, the fetch-execute cycle written formally, and assembly language.
- Click the stages below in the order they happen.
//The fetch–execute cycle in register transfer notation
AS asks for this formally. Learn the notation: square brackets mean 'the contents of'.
MAR ← [PC] address of next instruction
PC ← [PC] + 1 point at the one after
MDR ← [[MAR]] fetch what is AT that address
CIR ← [MDR] move it to the instruction register
decode, then execute//Bus widths decide the limits
The address bus width sets how much memory can be addressed: n lines gives 2ⁿ locations, so 16 lines addresses 65 536 locations. The data bus width sets how many bits move at once. The address bus is one-way from the CPU; the data and control buses are two-way.
//Addressing modes
Immediate: the operand IS the value. Direct: the operand is the address holding the value. Indirect: the operand is the address of an address. Indexed: the address plus the contents of an index register — used for stepping through an array.
LDM #20 immediate -> load the number 20
LDD 20 direct -> load what is stored at address 20
LDI 20 indirect -> address 20 holds another address
LDX 20 indexed -> address 20 + index register//Interrupts
At the END of each fetch-execute cycle the processor checks for an interrupt. If one is flagged, the current register contents are pushed onto a stack, the interrupt service routine runs, and then the contents are popped back so work continues exactly where it stopped.
CHECK YOURSELF
1.An address bus has 16 lines. How many memory locations can it address?
2.In LDM #20, what does the processor load?