IGCSE1.3.1Paper 1 — Computer Systems

Computer Architecture

What is inside the processor, and the cycle it repeats billions of times a second.

YOU SHOULD BE ABLE TO

Describe the role of the CPU.
Describe the von Neumann model: ALU, control unit, registers and buses.
Describe the purpose of the MAR, MDR, program counter and accumulator.
Describe the fetch–decode–execute cycle.
Explain how clock speed, cache size and number of cores affect performance.
Describe embedded systems and give examples.

A processor — where the fetch–execute cycle happensCC0 1.0

A RAM module — volatile main memoryTim Sullivan · CC0 1.0

The motherboard everything plugs intoKurt Kaiser · CC0

PUT IT IN ORDER0/6

Click the stages below in the order they happen.

//Fetch–decode–execute, in the right order

Learn this as a list. Questions often give you the steps jumbled and ask you to order them, or name which register is used at a given step.

FETCH
  1. The address in the PC is copied to the MAR
  2. The instruction at that address is fetched into the MDR
  3. The PC increases by 1, ready for the next instruction

DECODE
  4. The control unit works out what the instruction means

EXECUTE
  5. The instruction is carried out
     (the ALU does it if it is a calculation;
      the result goes to the accumulator)

//The three buses

Address bus: carries addresses, and is ONE-WAY (from the CPU). Data bus: carries the actual data, and is TWO-WAY. Control bus: carries control signals such as read/write, and is two-way.

//Making a computer faster

Higher clock speed = more cycles per second = more instructions. More cores = genuinely different instructions at the same time. Bigger cache = more frequently used data kept close to the CPU, so less waiting for slow RAM. Always explain WHY, not just what.

//Embedded systems

A computer built into a larger device to do one dedicated job: a washing machine, a microwave, traffic lights, a car engine management system. They are cheap, small, low-power and reliable, but usually hard to upgrade.

KEY TERMS

FLASHCARDS1 / 6

IN THE EXAM

'Explain how increasing cache improves performance' needs the chain: more data stored near the CPU → fewer fetches from RAM → RAM is slower → so the CPU waits less.

CHECK YOURSELF

1.Which register holds the address of the NEXT instruction?

2.In the fetch stage, what is copied into the MAR?

3.Why does a larger cache make a computer faster?